Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction. Since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens;” however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens.” Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). As the critical dimensions of the target patterns become increasingly smaller, it is becoming increasingly harder to reproduce the target patterns on the wafer. However, there are known techniques that allow for a reduction in the minimum CD that can be imaged or reproduced in a wafer. One such technique is the double exposure technique wherein features in the target pattern are imaged in two separate exposures.
For example, one commonly known double exposure technique is dipole illumination. In this technique, during a first exposure the vertical edges of the target pattern (i.e., features) are illuminated and then during a second exposure the horizontal edges of the target pattern are illuminated. As noted, by utilizing two exposures, improved imaging performance may be obtained.
In addition, the use of scattering bars “SB” (or assist features “AF”) has become indispensable as chip manufacturers move to more aggressive design rules and lower k1 factors in production. The width “d” of the SB can be estimated using the following equation, where kSB is a scaling constant to indicate non-printability or sub-resolution (a typical range of the SB scaling factor kSB is 0.2-0.25):d=kSB(λ/NA),
where λ is the wavelength of the exposure tool, and NA is the numerical aperture of the exposure tool.
In order to maintain k1 above 0.35, manufacturers tend to use a higher NA exposure tool. With the advent of immersion lithography, the NA value can be made greater than 1. Under such hyper NA conditions, SB scalability and printability are becoming a critical issue. FIG. 1a plots the allowable SB width versus the half pitch minimum design rule. The secondary axis is the k1 factor. As indicated by FIG. 1a, as device manufacturers move to lower k1 production, the SB width needs to also scale down accordingly in order to avoid unwanted printing of the SBs. This presents a problem in that at some point the required width of the SB to avoid printing will be smaller than the minimum manufacturable width (i.e., the required SB will be too small to manufacture).
Moreover, as the SB width on reticles becomes smaller than the exposure wavelength, λ, the Kirchoff scalar theory is no longer valid. FIG. 1b illustrates a comparison of a simulated aerial image of an isolated line using 0.85 NA and QUASAR illumination. The SB width on 4× reticle is 60 nm on a BIM (i.e., bright intensity binary mask). Referring to FIG. 1b, comparing the aerial image for rigorous EMF (NA85QS9363rig) versus scalar (NA85QS9363scl), the EMF aerial image indicates that the SB is actually darker than the scalar image predicted. This suggests that SBs have more optical weight and are therefore more readily/easily printable on wafers. Accordingly, there is a need for a process which addresses the SB scalability and printability and prevents the printing of SBs.